DRAMs (dynamic random access memory) and other volatile semiconductor memories are constructed in this manner. They have a memory cell array whose memory cells each have a storage capacitor for storing charges and a selection transistor. Each memory cell is actuated by a first line (for example, a bit line) and a second line (e.g., a word line), which runs at right angles or obliquely to the first line over the semiconductor substrate and crosses the first line. By altering the electrical potentials on the first and/or the second line, the selection transistor can be switched, so that a certain quantity of charge can flow into or out of the storage capacitor.
Selection transistors are usually in the form of MOSFETs (metal oxide semiconductor field effect transistor), the first source/drain electrode of which is connected to a bit line and the gate electrode of which is connected to a word line. The second source/drain electrode is routed to the storage capacitor. In view of the increasing integration density of future semiconductor memories, the selection transistors are produced in the form of vertical transistors whose two source/drain electrodes are arranged one above the other vertically with respect to the substrate surface. This means that the selection transistor requires only a minimal substrate base area. In vertical selection transistors, the gate electrode is arranged with just a slight lateral offset and at a central level between the two source/drain electrodes of the transistor. By contrast, planar selection transistors, whose electrodes are arranged laterally next to one another on the substrate surface, require a much larger substrate base area.
The cell array of a semiconductor memory contains storage capacitors arranged, with respect to the base area of the semiconductor substrate, in direct proximity to the crossing point between the bit line and the word line, which actuate the memory cell in question. In line with the usual network-type arrangement of mutually parallel bit lines and mutually parallel word lines, which usually run at right angles to the bit lines over or in the substrate base area, the memory cells and hence also the storage capacitors are arranged on the substrate in the manner of a chessboard, for example. At least one edge of the cell array is provided with connections for the word lines crossing the bit lines. In the case of a real cell array architecture, by contrast, the bit lines no longer cross all the word lines, but rather just a few of them to keep down the bit line capacitance and to simplify the reading of an information item from a memory cell. Various groups of word lines therefore cross different groups of bit lines, which means that a plurality of cell blocks are produced, instead of a single cell array. For word lines and bit lines, corresponding driver circuits, i.e., word line drivers or evaluation circuits for bit lines, are used.
During operation of a semiconductor memory, time delays arise which vary depending on the length of the lines via which electrical signals are transported. Since semiconductor memories are operated at an increasing clock rate, the time delays for various signals can be controlled and coordinated with respect to one another. In particular, time delays caused by different line lengths need to be significantly below the clock rate at which a semiconductor memory is operated in order to ensure that memory operation works correctly. However, increased clock rates, i.e., ever shorter intervals of time between clock pulses, mean that the increased size of memory cell arrays results in errors on account of different line lengths, particularly in word lines and bit lines. The more memory cells are connected to a single word line or bit line, the greater the time difference for a signal, which is produced via these lines when writing or reading to or from the memory cells or when activating or deactivating rows of memory cells. Since word lines and bit lines are connected (by a driver circuit) to a logic area, which controls the operation of the memory cell array, the signal delays vary approximately proportionally to the distance between a memory cell addressed via a line and the logic area. Thus, for example, memory cells arranged close to a bit line driver tend to be read more quickly than memory cells which are situated at the opposite end of the bit line. The same applies to the signal propagation along word lines. Particularly in the case of radio frequency circuits, which are operated at clock rates in the gigahertz range, the correct operation of a semiconductor memory requires particularly uniform signal delays.